The classic PCB design methodology of creating a schematic, placing components, routing traces and then verifying/testing the design with a number of prototype iterations results in delays. These delays are no longer acceptable in today's environment of time-to-market pressure.

Our PCB design methodology will ensure product performance, time-to-market, unit cost and manufacturing yield requirements are met. Layer 16 will simulate to provide a 'right first time' guarantee in the critical areas of impedence, crosstalk and signal integrity. This exercise will remove the impact of rework on cost and time scales. Our simulation results will allow design steps to be taken that significantly reduce design risk.

Typical work includes:
- Working with customers to develop and understand system environment
- Developing critical signal quality checks
- Identify critical timing requirements
- Build libraries (IO buffers, Interconnect, Package, Connectors)
- 2-D/3D electromagnetic modeling
- Pre-/post-layout power system design and analysis
- I/O buffer selection
- Topology and termination definition
- Clock system design/review
- Pre-layout solution space analysis
- Define decoupling strategy
- Develop physical and electrical design rulesPost-layout verification
- Power integrity analysis

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